A/Level ICT - Fetch Execute Cycle (CPU)
Subject: Information & Communication Technology (ICT)
Topic: CPU Architecture & Instruction Cycle
Syllabus: A/Level (Local Syllabus)
Download this comprehensive short note on the Fetch-Decode-Execute Cycle. This PDF explains how the CPU retrieves instructions from memory, decodes them using the Control Unit, and executes them. It covers the function of the Program Counter (PC), Memory Address Register (MAR), and Current Instruction Register (CIR).
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What you need to know for the Exam:
- Fetch: The PC holds the address of the next instruction, which is copied to the MAR.
- Decode: The instruction is sent to the CIR and decoded by the Control Unit.
- Execute: The ALU performs calculations, or data is moved to memory.
- Registers: You must memorize the definitions of PC, MAR, MDR, CIR, and ACC.
Exam Tip: In the structured essay paper, you are often asked to draw the flow of data between registers. Use this note to practice that diagram.
Keywords: Von Neumann Architecture, CPU Registers, A/L ICT Past Papers, System Bus, Sri Lanka Education.